1. Field
Exemplary embodiments of the present invention relate to a pulse generation circuit, a burst order control circuit, and a data output circuit.
2. Description of the Related A
Data input/output operations of a synchronous type semiconductor memory device are performed in synchronization with an internal clock, which is generated on the basis of an external clock. Kinds of such a synchronous type semiconductor memory device include an SDR (single data rate) SDRAM (synchronous dynamic random access memory), which outputs data only at the rising edge of a clock, a DDR (double data rate) SDRAM, which outputs data at the both of rising and falling edge of a clock, a DDR2 SDRAM, and a DDR3 SDRAM.
The DDR3 SDRAM generally adopts an 8-bit prefetch scheme. According to the 8-bit prefetch scheme, per read command, 8-bit data are outputted in parallel from a memory cell array, and then the 8-bit data are outputted in series through one data input/output pin to an outside during two clock cycles.
The device outputs the data in series with the controlled order according to a seed address and a burst mode, where burst order control controls the output order of data. The burst order control generates pulses respectively corresponding to a plurality of global lines such that the data, outputted to the plurality of global lines with the controlled order, and stored in pipe latches, are transferred to data lines of a next stage, For the burst order control, the pulses corresponding to the output lines of a plurality of latches are activated in the controlled order. With such burst order control, the data output circuit controls the order of data output.
A conventional data output circuit includes 24 D flip-flops and generates pulses for burst order control of 8 data by simultaneously operating the 24 D flip-flops. High power and current consumption are concerns related to the prior art, because many D flip-flops are simultaneously operated for the burst order control.
That is to say, in the conventional art, a problem may be caused in that, as the large number of D flip-flops are simultaneously activated to generate the plurality of pulse signals which are activated in the order that is specified according to the seed address and the burst mode, current and power consumption increases.